All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction

Yi Ping Kuo, Po-Tsang Huang, Chung Shiang Wu, Yu Jie Liang, Ching Te Chuang, Yuan Hua Chu, Wei Hwang

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

In this paper, an all-digitally controlled linear voltage regulator is proposed for ultra-low-power event-driven sensing platforms using a PMOS strength self-calibration technique. The voltage regulator generates the output voltage from 0.43V to 0.55V in steps of 30mV with a supply voltage of 0.6V. Against PVT and loading current variations, the PMOS strength self-calibration circuitry utilizes a voltage-detected coarse tune and a timing-detected fine tune for output ripple reduction. The coarse tune is designed to suppress the output voltage within the fine-tune region via a comparator-based error detector. Accordingly, the fine tune block detects the PMOS turn-on ratio in a specific time window for further reducing the output ripple. This linear voltage regulator is implemented using TSMC 65nm LP CMOS process. The simulation results show the best improvement of ripple reduction by 81%. Moreover, ns-order voltage transition time and the best (lowest) FOM of 0.76 pA·s can be realized.

原文English
主出版物標題2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781479962754
DOIs
出版狀態Published - 28 五月 2015
事件2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 - Hsinchu, Taiwan
持續時間: 27 四月 201529 四月 2015

出版系列

名字2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

Conference

Conference2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
國家Taiwan
城市Hsinchu
期間27/04/1529/04/15

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