All digital phase-locked loop with modified binary search of frequency acquisition

Shyh-Jye Jou*, Ya Lan Tsao, I. Ying Yang

*Corresponding author for this work

研究成果: Paper同行評審

3 引文 斯高帕斯(Scopus)

摘要

In this paper, the design of an all digital phase-locked loop is proposed. The phase-lock process is separated into frequency acquisition and phase acquisition that significantly reduces the phase-lock time. By using a modified binary search algorithm, it can accomplish phase lock process within 43 input clock cycles. To generate a high frequency digital clock, a digitally controlled oscillator with 14-bits is used. The DCO frequency range is from 250 MHz to over 500 MHz. The whole chip contains about 5000 transistors and the core chip size is 1.2*1.2 mm2.

原文English
頁面195-198
頁數4
DOIs
出版狀態Published - 1 十二月 1998
事件Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology - Lisboa, Portugal
持續時間: 7 九月 199810 九月 1998

Conference

ConferenceProceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology
城市Lisboa, Portugal
期間7/09/9810/09/98

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