All-Digital Mismatched Calibrator and Compensator for SR Latch-Based Variable-Gain Time Amplifier

Kuan Chieh Chao, Jung Chin Lai, Terng Yin Hsu*

*Corresponding author for this work

研究成果: Article同行評審

摘要

Two major mismatches in SR latch-based time amplifiers (TA) include input skew, which causes gain imbalance, and loading mismatch, which reduces gain accuracy. Accordingly, we propose an all-digital mismatched self-calibrator and compensator for an SR latch-based variable-gain TA. Tunable matching cells and variable capacitors are built into TAs to compensate for input skew (gain imbalance) and loading mismatch (gain inaccuracy). To ensure that the proposed calibration works efficiently and accurately, the TA must provide at least high and low gains where the low gain calibrates the most significant bit (MSB) and the high gain calibrates the least significant bit (LSB). This self-calibrator costs 4375 gates, and the power consumption is 2.8 mA for the TA gain with 2 and 3.2 mA for the TA gain with 16 at a sampling rate of 10 MHz.

原文English
文章編號9020137
頁(從 - 到)42082-42096
頁數15
期刊IEEE Access
8
DOIs
出版狀態Published - 2 三月 2020

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