Aggregating and Disaggregating Packets with Various Sizes of Payload in P4 Switches at 100 Gbps Line Rate

Shie-Yuan Wang*, Jun Yi Li, Yi-Bing Lin

*Corresponding author for this work

研究成果: Article同行評審

2 引文 斯高帕斯(Scopus)

摘要

Aggregating multiple small packets into a large packet provides many advantages. For example, multiple small packets can share a single copy of common Ethernet/IP/UDP headers to reduce the percentage of network bandwidth spent on transmitting headers. In the past, packet aggregation and disaggregation were done by a server CPU or a switch CPU, resulting in low throughputs. In this paper, we design and implement packet aggregation and disaggregation functions in the packet processing pipelines of P4 switches. Our novel designs allow packets with various sizes of payload to be aggregated and disaggregated purely in the data plane of a P4 switch. Experimental results show that the achieved throughputs of our aggregation and disaggregation methods can reach 100 Gbps, which is the line rate of the used P4 switch.
原文English
文章編號102676
期刊Journal of Network and Computer Applications
165
DOIs
出版狀態Published - 1 九月 2020

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