AES-based security coprocessor IC in 0.18-μm CMOS with resistance to differential power analysis side-channel attacks

David D. Hwang*, Kris Tiri, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede

*Corresponding author for this work

研究成果: Article同行評審

102 引文 斯高帕斯(Scopus)

摘要

Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18-μm CMOS consisting of an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint-matching engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DFA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1500 000 encryptions.

原文English
頁(從 - 到)781-790
頁數10
期刊IEEE Journal of Solid-State Circuits
41
發行號4
DOIs
出版狀態Published - 1 四月 2006

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