Soft error rate (SER) has become a critical reliability is- sue for CMOS designs due to continuous technology scaling. However, the striking-time and multi-cycle effects have not been properly considered in SER for advanced CMOS de- signs. Therefore, in this paper, the striking-time and multi- cycle effects are formulated into the problem of SER esti- mation, and then a SER analysis framework is proposed, accordingly. Experimental results show that SERs on the benchmark circuits are seriously underestimated when ig- noring both effects. Moreover, SERs increase more on those high-performance or low-power CMOS designs. New treat- ment to SER needs to be explored in the future.