ADC clock jitter measurement and correction using a stochastic TDC

Chi Wei Fan*, Jieh-Tsorng Wu

*Corresponding author for this work

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

The jitter of the sampling clock of an analog-to-digital converter (ADC) is measured by a stochastic time-to-digital converter (TDC). The measured jitter data are used to correct the ADC sampling error and improve its signal-to-noise ratio (SNR). The same ADC is used to calibrate the TDC in the background. Both the TDC and the ADC operate at a sampling rate of 80 MS/s. Fabricated in a 65 nm CMOS technology, the TDC consists of 127 timing comparators. The proposed jitter correction technique achieves an equivalent sampling jitter root-mean-squared value (rms) of 4 ps when the jitter rms of the original sampling clock is 8.2 ps.

原文English
主出版物標題Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
頁面1007-1010
頁數4
DOIs
出版狀態Published - 1 十二月 2010
事件2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur, Malaysia
持續時間: 6 十二月 20109 十二月 2010

出版系列

名字IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

Conference2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
國家Malaysia
城市Kuala Lumpur
期間6/12/109/12/10

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  • 引用此

    Fan, C. W., & Wu, J-T. (2010). ADC clock jitter measurement and correction using a stochastic TDC. 於 Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 (頁 1007-1010). [5774884] (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2010.5774884