Active device under bond pad to save I/O layout for high-pin-count SOC

Ming-Dou Ker, Jeng Jie Peng, Hsin Chin Jiang

研究成果: Conference contribution同行評審

4 引文 斯高帕斯(Scopus)

摘要

To save layout area for electrostatic discharge (ESD) protection design in the SOC era, test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35 μm one-poly-four-metal (1P4M) 3.3V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the effect of bonding stress on the active devices under the pads. Threshold voltage, off-state drain current, and gate leakage current of these devices under bond pads have been measured. After assembled in wire bond package, the measurement results show that there are only little variations between devices under bond pads and devices beside bond pads. This result can be applied on saving layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count system-on-a-chip (SOC).

原文English
主出版物標題Proceedings of the 2003 4th International Symposium on Quality Electronic Design, ISQED 2003
發行者IEEE Computer Society
頁面241-246
頁數6
ISBN(電子)0769518818
DOIs
出版狀態Published - 1 一月 2003
事件2003 4th International Symposium on Quality Electronic Design, ISQED 2003 - San Jose, United States
持續時間: 24 三月 200326 三月 2003

出版系列

名字Proceedings - International Symposium on Quality Electronic Design, ISQED
2003-January
ISSN(列印)1948-3287
ISSN(電子)1948-3295

Conference

Conference2003 4th International Symposium on Quality Electronic Design, ISQED 2003
國家United States
城市San Jose
期間24/03/0326/03/03

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