Interconnect models were proposed to translate the analog behavior of interconnect coupling noise into digital output and reveal the actual waveform without uncertainties arising from parasitics in direct probing. A4-metal layer test chip was fabricated to demonstrate the use of in-situ measurement technique to evaluate subnanosecond on-chip coupling effects. Time domain technique was used to measure the signal delay for a wide range comparator (WRC) circuit implemented to capture transient waveforms. The analysis suggested increase in the driver size and reduction in the peak delay change as well as the noise pulse width.
|頁（從 - 到）||226-227|
|期刊||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|出版狀態||Published - 1 十二月 2000|
|事件||2000 IEEE International Solid-State Circuits Conference 47th Annual ISSCC - San Francisco, CA, United States|
持續時間: 7 二月 2000 → 9 二月 2000