This paper proposes an on-wafer test circuitry for rapidly and accurately characterizing the devices under tests (DUTs) of the DUT array in the wafer acceptance test (WAT) to qualify wafers faster and more reliably. The proposed test cell simply comprises a DUT and a selection MOSFET operating in the saturation region as a current buffer when being activated. An analog feedback loop with a replica-biasing circuit tracks the selected DUT's output current and automatically biases the selection MOSFET's gate so as to accurately duplicate the desired setup voltage at the selected DUT's output node. Comparing with conventional designs using the Kelvin sensing scheme to address the switches' IR drops, the proposed design has less transistor counts, shorter test time, and no risk of forward-bias p-n junctions. Consequently, it achieves a lower test cost and a higher test throughput. The whole proposed test circuitry including 1024 NMOS DUTs has been designed and fabricated in 90-nm CMOS. The active area is only 60μm by 800μm which is small enough to be placed into the scribe line on wafers as conventional WAT circuitry is. Measurement results demonstrate the proposed design's efficiency and capability of revealing local process variations.
|頁（從 - 到）||3467-3479|
|期刊||IEEE Transactions on Circuits and Systems I: Regular Papers|
|出版狀態||Published - 1 九月 2019|