A wide-range burst mode clock and data recovery circuit

Wei-Zen Chen*, Chin Yuan Wei, Jen Wen Chen

*Corresponding author for this work

研究成果: Paper同行評審

2 引文 斯高帕斯(Scopus)

摘要

This paper describes the design of a 0.625-3.125 Gbps, burst mode clock and data recovery circuit in a 0.18 μm CMOS process. A novel bang-bang PD incorporating binary-search phase acquisition and dynamic loop filter is proposed to achieve rapid phase locking. The measured locking time is less than 1 ns (@ 3.125 Gbps). Integrating with a limiting amplifier and a 1 to 4 demultiplexer on a single chip, the total power dissipation is 78 mW. The input sensitivity of the burst mode receiver is about 30 mV for BER less than 10 -10.

原文English
頁面403-406
頁數4
DOIs
出版狀態Published - 1 十二月 2006
事件2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China
持續時間: 13 十一月 200615 十一月 2006

Conference

Conference2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
國家China
城市Hangzhou
期間13/11/0615/11/06

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