This paper describes the design of a 0.625-3.125 Gbps, burst mode clock and data recovery circuit in a 0.18 μm CMOS process. A novel bang-bang PD incorporating binary-search phase acquisition and dynamic loop filter is proposed to achieve rapid phase locking. The measured locking time is less than 1 ns (@ 3.125 Gbps). Integrating with a limiting amplifier and a 1 to 4 demultiplexer on a single chip, the total power dissipation is 78 mW. The input sensitivity of the burst mode receiver is about 30 mV for BER less than 10 -10.
|出版狀態||Published - 1 十二月 2006|
|事件||2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China|
持續時間: 13 十一月 2006 → 15 十一月 2006
|Conference||2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006|
|期間||13/11/06 → 15/11/06|