A vario-power ME architecture using content-based subsample algorithm

Hsien Wen Cheng*, Lan-Rong Dung

*Corresponding author for this work

研究成果: Article同行評審

5 引文 斯高帕斯(Scopus)

摘要

The Motion estimator is a key element in many video compression systems and it tends to dominate the power consumption in them. With increasing demand of portable, power-aware multimedia devices, an architecture that can be flexible in both power consumption and compression quality is essential. To meet this requirement, this paper presents a novel power-aware architecture, called the Vario-Power Architecture, for the motion estimation. Based on a semi-systolic array with the content-based subsample algorithm, the architecture real-time disables some processing elements to reduce power consumption. By performing the edge extraction first, a threshold is then set as the criterion of whether to enable or disable processing elements and thus the switch activities of the system can be reduced. As the simulation shows, the architecture may operate at different power consumption modes according to the remaining capacity of the battery pack giving little quality degradation and the power overhead under 0.36%.

原文English
頁(從 - 到)349-354
頁數6
期刊IEEE Transactions on Consumer Electronics
50
發行號1
DOIs
出版狀態Published - 1 二月 2004

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