A variable partitioning algorithm of BDD for FPGA technology mapping

Jie Hong Jiang*, Jing Yang Jout, Juinn-Dar Huang, Jung Shian Wei

*Corresponding author for this work

研究成果: Article同行評審

4 引文 斯高帕斯(Scopus)

摘要

Field Programmable Gate Arrays (FPGA's) are important devices for rapid system prototyping. Roth-Karp decomposition is one of the most popular decomposition techniques for Look-Up Table (LUT)-based FPGA technology mapping. In this paper, we propose a novel algorithm based on Binary Decision Diagrams (BDD's) for selecting good lambda set variables in Roth-Karp decomposition to minimize the number of consumed configurable logic blocks (CLB's) in FPGA's. The experimental results on a set of benchmarks show that our algorithm can produce much better results than the similar works of the previous approaches [1], [4].

原文English
頁(從 - 到)1813-1819
頁數7
期刊IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E80-A
發行號10
出版狀態Published - 1 一月 1997

指紋 深入研究「A variable partitioning algorithm of BDD for FPGA technology mapping」主題。共同形成了獨特的指紋。

引用此