A unified model for partial-depletion and full-depletion SOI circuit designs: Using BSIMPD as a foundation

Pin Su*, Samuel K.H. Fung, Peter W. Wyatt, Hui Wan, Mansun Chan, Ali M. Niknejad, Chen-Ming Hu

*Corresponding author for this work

研究成果: Conference article同行評審

16 引文 斯高帕斯(Scopus)

摘要

We present our approach to developing a unified SOI MOSFET model for circuit designs using state-of-the-art SOI technologies. Using BSIMPD as a foundation, we unify the PD and FD models by the concept of body-source built-in potential lowering. This unification is crucial due to the coexistence of PD/FD devices in a single chip as well as the coexistence of PD/FD behavior in a single device. The unified BSIMSOI model has been implemented in Berkeley SPICE3f4 and many commercial circuit simulators.

原文English
頁(從 - 到)241-244
頁數4
期刊Proceedings of the Custom Integrated Circuits Conference
DOIs
出版狀態Published - 19 十一月 2003
事件Proceedings of the IEEE 2003 Custom Integrated Circuits Conference - San Jose, CA, United States
持續時間: 21 九月 200324 九月 2003

指紋 深入研究「A unified model for partial-depletion and full-depletion SOI circuit designs: Using BSIMPD as a foundation」主題。共同形成了獨特的指紋。

引用此