A two-level pipelined systolic array chip for computing the discrete cosine transform

Jiun-In Guo, Chi Min Liu, Chein Wei Jen

研究成果: Conference contribution

摘要

A two-level pipelined systolic array chip for the discrete cosine transform (DCT) is presented. This chip is based on a new memory-based systolic algorithm which not only uses small ROM's and adders to realize the multiplications but also owns good data locality. Therefore, this chip possesses outstanding performance in hardware cost, computing speeds, the number of I/O channels, and the I/O bandwidth.

原文English
主出版物標題1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers
發行者Institute of Electrical and Electronics Engineers Inc.
頁面199-203
頁數5
ISBN(電子)0780309782
DOIs
出版狀態Published - 1 一月 1993
事件1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Taipei, Taiwan
持續時間: 12 五月 199314 五月 1993

出版系列

名字International Symposium on VLSI Technology, Systems, and Applications, Proceedings
ISSN(列印)1930-8868

Conference

Conference1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993
國家Taiwan
城市Taipei
期間12/05/9314/05/93

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  • 引用此

    Guo, J-I., Liu, C. M., & Jen, C. W. (1993). A two-level pipelined systolic array chip for computing the discrete cosine transform. 於 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers (頁 199-203). [263606] (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VTSA.1993.263606