A study on poly-Si thin-film transistor (TFT) SONOS memory cells with source/drain engineering

Bing-Yue Tsui*, Jui Yao Lai

*Corresponding author for this work

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

Poly-Si thin-film transistor SONOS memory cells with various source/drain junctions are studied comprehensively. For pure Schottky-barrier junction, the overlap between source/drain and gate is critical. A 2-nm underlap results in high tunneling resistance and thus poor programming efficiency. Suitable designed modified-Schottky-barrier junction can improve programming speed by Fowler-Nordheim tunneling while keeping erase and retention performance unaltered. The main degradation mechanism during endurance test is attributed to interface state generation and tunneling layer degradation. After improving the quality of the tunneling layer, the modified Schottky barrier junction would be a promising choice for 3-dimentional poly-Si memory.

原文English
主出版物標題ESSDERC 2011 - Proceedings of the 41st European Solid-State Device Research Conference
頁面199-202
頁數4
DOIs
出版狀態Published - 12 十二月 2011
事件41st European Solid-State Device Research Conference, ESSDERC 2011 - Helsinki, Finland
持續時間: 12 九月 201116 九月 2011

出版系列

名字European Solid-State Device Research Conference
ISSN(列印)1930-8876

Conference

Conference41st European Solid-State Device Research Conference, ESSDERC 2011
國家Finland
城市Helsinki
期間12/09/1116/09/11

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