A new background calibration technique is described to digitally trim the input-referred offset voltage of comparators in a high-speed flash analog-to-digital converters. The polarity of comparator's offset is detected by observing the output code density of a random chopping comparator. Binary feedback is used to adjust the comparator's offset. All calibration processing is performed in the digital domain, thus minimizing the overhead for analog circuitry. Two key design parameters are the comparator's trimming step and the thresholds of a peak detector, which determine the offset's standard deviation and the time constant of the calibration loop.
|期刊||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版狀態||Published - 7 九月 2004|
|事件||2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada|
持續時間: 23 五月 2004 → 26 五月 2004