A statistical background calibration technique for flash analog-to-digital converters

Chun Cheng Huang; Jieh-Tsorng Wu

doi:10.1109/ISCAS.2004.1328147

A statistical background calibration technique for flash analog-to-digital converters

Chun Cheng Huang^*, Jieh-Tsorng Wu

^*Corresponding author for this work

電子工程學系

研究成果: Conference article › 同行評審

3 引文斯高帕斯（Scopus）

摘要

A new background calibration technique is described to digitally trim the input-referred offset voltage of comparators in a high-speed flash analog-to-digital converters. The polarity of comparator's offset is detected by observing the output code density of a random chopping comparator. Binary feedback is used to adjust the comparator's offset. All calibration processing is performed in the digital domain, thus minimizing the overhead for analog circuitry. Two key design parameters are the comparator's trimming step and the thresholds of a peak detector, which determine the offset's standard deviation and the time constant of the calibration loop.

原文	English
期刊	Proceedings - IEEE International Symposium on Circuits and Systems
卷	1
DOIs	https://doi.org/10.1109/ISCAS.2004.1328147
出版狀態	Published - 7 九月 2004
事件	2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada 持續時間: 23 五月 2004 → 26 五月 2004

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10.1109/ISCAS.2004.1328147

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AB - A new background calibration technique is described to digitally trim the input-referred offset voltage of comparators in a high-speed flash analog-to-digital converters. The polarity of comparator's offset is detected by observing the output code density of a random chopping comparator. Binary feedback is used to adjust the comparator's offset. All calibration processing is performed in the digital domain, thus minimizing the overhead for analog circuitry. Two key design parameters are the comparator's trimming step and the thresholds of a peak detector, which determine the offset's standard deviation and the time constant of the calibration loop.

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