A spread spectrum clock generator for SATA-II

Wei Ta Chen, Jen Chien Hsu, Hong Wen Lune, Chau-Chin Su

研究成果: Conference article同行評審

26 引文 斯高帕斯(Scopus)

摘要

In this paper, we proposed a spread spectrum clock generator (SSCG) for the Serial AT Attachment Generation 2 (SATA-II). We use a fractional-N PLL to accomplish the spread spectrum function. The SSCG integrates a conventional PLL, a digital 3rd order MASH 1-1-1 delta-sigma modulator and an address generator. The SSCG generates clocks at 1.5 GHz, a 5000 ppm down spread with a triangular waveform frequency modulation of 33 KHz. The circuit has been simulated in 0.18 um CMOS technology. The non spread spectrum clocking has a jitter of 80ps and the peak amplitude reduction is 23.44 dBm in spread spectrum mode. The power dissipation from a 1.8V supply is 55 mW.

原文English
文章編號1465169
頁(從 - 到)2643-2646
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
DOIs
出版狀態Published - 23 五月 2005
事件IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
持續時間: 23 五月 200526 五月 2005

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