In this paper, a speed and power-efficient set partitioning in hierarchical trees (SPIHT) design is introduced for one-dimensional (1-D) wavelet-based electrocardiography (ECG) compression systems with quality guarantee. To achieve real-time and low-power design objectives toward wearable quality-on-demand (QoD) ECG applications, we first propose a coding-time-and computation-efficient SPIHT algorithm using various types of coding status register files to overcome the disadvantages of low coding speeds and complicated hardware architectures characterizing prior SPIHT algorithms resulting from the necessity of dynamic computation and arrangement in the sorting and refinement processing phase. Second, a highly pipelined and power-efficient very large scale integration (VLSI) architecture is developed to implement a high-performance and low-power SPIHT design based on the proposed algorithm. The final simulation results demonstrate that our proposed algorithm can speed up the average coding time 1.52 to 2.74 times compared to prior work with an identical compression ratio for an 11-level 1024 x 1 1 - D discrete wavelet transform at diverse target percentage root-mean-square differences (PRDT) on various MIT-BIH arrhythmia datasets. Applied to wearable wavelet-based QoD ECG applications, our proposed VLSI architecture attains a working frequency of 740 MHz and consumes an average of 23 mu W of power with Taiwan Semiconductor Manufacturing Company 90-nm CMOS technology, which shows the effectiveness of speed and power over the state-of-the-art designs.