A scalable digitalized buffer for gigabit I/O

Hung Wen Lu*, Chau-Chin Su, Chien-Nan Liu

*Corresponding author for this work

研究成果: Article同行評審

6 引文 斯高帕斯(Scopus)

摘要

A serial input-output (I/O) composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the simultaneous switching noise simultaneously. With a TSMC 0.18-μm CMOS process, the I/O occupies an area of 0.014 mm2 and operates from 4 Gbps.9 V to 1.5 Gbps.1 V.

原文English
頁(從 - 到)1026-1030
頁數5
期刊IEEE Transactions on Circuits and Systems I: Regular Papers
55
發行號10
DOIs
出版狀態Published - 1 十月 2008

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