A robust background calibration technique for switched-capacitor pipelined ADCs

Jen Lin Fan, Jieh-Tsorng Wu

研究成果: Conference article同行評審

1 引文 斯高帕斯(Scopus)

摘要

This work presents a robust background calibration scheme for switched-capacitor (SC) pipelined analog-to-digital converters. A SC multiplying digital-to-analog converter (MDAC) is usually linearized by high-gain capacitive feedback. Its conversion gain can be measured by splitting the input sampling capacitor and injecting a random sequence into the signal path. The magnitude of the random sequence can be extracted later in the digital domain. The use of input-dependent generation of the random sequence can eliminate the extra signal range requirement and also save calibration time. Furthermore, the use of random choppers to scramble signal can ensure that all necessary calibration data can be collected within a given time regardless of input conditions, resulting in a more robust ADC.

原文English
文章編號1464852
頁(從 - 到)1374-1377
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
DOIs
出版狀態Published - 1 十二月 2005
事件IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
持續時間: 23 五月 200526 五月 2005

指紋 深入研究「A robust background calibration technique for switched-capacitor pipelined ADCs」主題。共同形成了獨特的指紋。

引用此