A resolution-reconfigurable and power scalable SAR ADC with partially thermometer coded DAC

Hao Min Lin*, Chih Hsuan Lin, Kuei-Ann Wen

*Corresponding author for this work

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)

摘要

Power consumption is becoming more and more important in the Internet of Things (IOT). The ADC is the main power hungry in multi-sensor electronic systems and effectively reducing ADC power consumption without affecting ADC characteristics is an important. This paper is extended from the conference paper. The segmented SAR ADC presents reconfigurable 9 to 12-bit DACs with rail-to rail input range, and 3 MSB segmented capacitor arrays are used to improve linearity and lower switching energy than conventional architectures. The dual supply voltage skill separating digital and analog voltage is implemented for achieving low power consumption. In the provided 9 to 12 bits mode, this structure consumes 2.5, 2.8, 3.9 and 9.7 uW and SNDR achieve 52.3, 57.7, 63.2 and 68.6 db respectively, resulting in figure of merit (FoM) 148, 88.8, 66.3 and 88.4 fJ/conversion-step.

原文English
頁(從 - 到)89-96
頁數8
期刊Advances in Science, Technology and Engineering Systems
3
發行號6
DOIs
出版狀態Published - 1 一月 2018

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