A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications

Win San Khwa, Meng Fan Chang, Jau Yi Wu, Ming Hsiu Lee, Tzu Hsiang Su, Keng Hao Yang, Tien-Fu Chen, Tien Yen Wang, Hsiang Pang Li, Matthew Brightsky, Sangbum Kim, Hsiang Lan Lung, Chung Lam

研究成果: Article同行評審

5 引文 斯高帕斯(Scopus)

摘要

For multilevel cell (MLC) phase change memory (PCM), resistance drift (R-drift) phenomenon causes cell resistance to increase with time, even at room temperature. As a result, the fixed-threshold-retention (FTR) raw-bit-error-rate (RBER) surpasses practical ECC correction ability within hours after being programmed. This study proposes a resistance drift compensation (RDC) scheme to mitigate R-drift issue. The proposed RDC scheme realizes PCM drift compensation and features RDC pulse to suppress ECC decoding failure. The proposed approach was validated using a 90-nm 128M cells PCM chip and an FPGA-based memory controller verification system. The MLC PCM FTR RBER has been suppressed by over 100×, thereby bringing it within ECC capability. The effectiveness of the RDC scheme was verified up to 106 cycles.

原文English
文章編號7551121
頁(從 - 到)218-228
頁數11
期刊IEEE Journal of Solid-State Circuits
52
發行號1
DOIs
出版狀態Published - 1 一月 2017

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