A Quick Intelligent Page-Programming Architecture and a Shielded Bitline Sensing Method for 3 V-Only NAND Flash Memory

Tomoharu Tanaka, Hiroshi Nakamura, Koji Sakui, Hideko Oodaira, Shirota Riichiro, Kazunori Ohuchi, Fujio Masuoka, Hisashi Hara

研究成果: Article

67 引文 斯高帕斯(Scopus)

摘要

This paper describes a quick intelligent page- programming architecture with a newly introduced intelligent verify circuit for 3 V-only NAND flash memories. The new verify circuit, which is composed of only two transistors, results in a simple intelligent program algorithm for 3 V-only operation and a reduction of the program time to 56%. This paper also describes a shielded bitline sensing method to reduce a bitline-bitline capacitive coupling noise from 700 mV to 35 mV. The large 700 mV noise without the shielded bitline architecture is mainly caused by the NAND-type cell array structure. A 3 V-only experimental NAND flash memory, developed in a 0.7-µm NAND flash memory process technology, demonstrates that the programmed threshold voltages are controlled between 0.4 V and 1.8 V by the new verify circuit. The shielded bitline sensing method realizes a 2.5-µS random access time with a 2.7-V power supply. The page-programming is completed after the 40-µs program and 2.8-µs verify read cycle is iterated 4 times. The block-erasing time is 10 ms.

原文English
頁(從 - 到)1366-1373
頁數8
期刊IEEE Journal of Solid-State Circuits
29
發行號11
DOIs
出版狀態Published - 1 一月 1994

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