The High Efficiency Video Coding (HEVC) standard provides superior compression with large and variable-size coding units and advanced prediction modes, which leads to high buffer costs, memory bandwidth, and irregular computation for ultra high-definition video decoding hardware. Thus, this paper presents an HEVC decoder with a four-stage mixed block size pipeline to reduce the pipeline stage buffer size by approximately 91% compared with the 64 × 64 block-based pipeline. The high memory bandwidth due to motion compensation problem was solved by 16 × 16 block-based data access, precision-based data access, and a smart buffer to reduce the data bandwidth by 88%. In addition, for irregular computation, a reconfigurable architecture was adopted to unify the variable-size transform. A common intra-prediction module was also designed with a 4 × 4 block-based bottom-up computation for variable-size intra prediction and modes in a regular manner. Furthermore, the corner position computation for the motion vector predictor was applied to handle variable-size motion compensation. Finally, the implementation with the TSMC 90-nm CMOS process used 467k logic gates and 15.778 kB of on-chip memory and supported 4096 × 2160 at 30-frames/s video decoding at a 270-MHz operation frequency.
|頁（從 - 到）||724-735|
|期刊||IEEE Transactions on Circuits and Systems for Video Technology|
|出版狀態||Published - 1 四月 2016|