A parallel multi-pattern PRBS generator and BER tester for 40+ Gbps serdes applications

Wei-Zen Chen*, Guan Sheng Huang

*Corresponding author for this work

研究成果: Conference contribution同行評審

5 引文 斯高帕斯(Scopus)

摘要

This paper presents the design of a programmable PRBS generator and a BER tester according to CCITT recommendations. Implemented in a parallel feedback configuration, this IC features PRBS generation of the sequences of length 27-l, 210-1, 215-1, 223-1, and 231-1 b for up to 40+Gbps serdes applications with 1:16 multiplexing and demultpilexing. The mark densities of 1/2, 1/4 and 1/8 for each of the patterns are also selectable. This IC could be used as a low cost substitute for more expensive bit error rate test system. Implemented in a 0.18 μm CMOS process, the total power dissipation is 141 mW.

原文English
主出版物標題Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
頁面318-321
頁數4
DOIs
出版狀態Published - 1 十二月 2004
事件Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits - Fukuoka, Japan
持續時間: 4 八月 20045 八月 2004

出版系列

名字Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits

Conference

ConferenceProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
國家Japan
城市Fukuoka
期間4/08/045/08/04

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