This paper presents the design of a programmable PRBS generator and a BER tester according to CCITT recommendations. Implemented in a parallel feedback configuration, this IC features PRBS generation of the sequences of length 27-l, 210-1, 215-1, 223-1, and 231-1 b for up to 40+Gbps serdes applications with 1:16 multiplexing and demultpilexing. The mark densities of 1/2, 1/4 and 1/8 for each of the patterns are also selectable. This IC could be used as a low cost substitute for more expensive bit error rate test system. Implemented in a 0.18 μm CMOS process, the total power dissipation is 141 mW.