A parallel-in folding technique for high-order FIR filter implementation

Lan-Rong Dung*, Hsueh Chih Yang

*Corresponding author for this work

研究成果: Article

摘要

This paper presents a hardware-efficient folding technique for high-order FIR filtering while considering the tradeoff between the number of processing elements and throughput rate. Given the throughput rate, one can always employ the minimum number of processing elements for saving the implementation cost and figure out a folded architecture. However, applying inefficient folding techniques may result in costly switches and registers. Therefore, our work intends to evaluate the efficiency for folding techniques in terms of the number of registers, and the power dissipation of registers. As shown in the estimation results, while comparing with the published folded architectures under the same throughput rate, the proposed folding technique can turn out less power dissipation and low hardware complexity than the others. The proposed design has been implemented using TSMC 0.18 μm 1P6M technology. As seen in the post-layout simulation, our design can meet the requirement of IS-95 WCDMA pulse shaping FIR filter while the power consumption can be as low as 16.66 mW.

原文English
頁(從 - 到)3659-3665
頁數7
期刊IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E89-A
發行號12
DOIs
出版狀態Published - 1 一月 2006

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