A numerical model for simulating MOSFET gate current degradation by considering the interface state generation

C. M. Yih, Steve S. Chung, C. C.H. Hsu

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

In this paper, a new gate current degradation model for n-MOSFET's by considering the interface state generation is proposed. This interface state has been characterized using a new approach and incorporated into a 2D device simulation for predicting the device gate current characteristics due to a hot carrier stress induced effect. Good agreement of the gate current has been achieved as compared with the measurement data for both fresh and stressed devices. This model is not only useful for predicting the gate current degradation, but also as a superior monitor to substrate current for submicron device reliability issues, in particular EPROM or flash EPROM devices.

原文English
主出版物標題1996 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 1996
發行者Institute of Electrical and Electronics Engineers Inc.
頁面115-116
頁數2
ISBN(電子)0780327454
DOIs
出版狀態Published - 1 一月 1996
事件1996 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 1996 - Tokyo, Japan
持續時間: 2 九月 19964 九月 1996

出版系列

名字International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Conference

Conference1996 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 1996
國家Japan
城市Tokyo
期間2/09/964/09/96

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