A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications

E. R. Hsieh, Y. C. Fan, K. Y. Chang, C. H. Liu, Chao-Hsin Chien, Steve S. Chung

研究成果: Conference contribution同行評審

摘要

A novel complementary tunneling FET (C-TFET) has been designed and targeted for the low power and appropriate performance applications (Apps). In this new architecture of C-TFET, the drain and source (D/S) are configured as a staggered structure to increase the tunneling current, and the conventional p-i-n junction C-TFET has been modified as a p-n junction to further enhance the Ion current. The results show that new design can achieve 310uA/um(n), 440uA/um(p) TFETs of Ion, comparable to those of LP planar CMOS devices, 0.1 nA/um of Ioff, while excellent S.S.(<10mV/dec) at Vdd= 0.7V, which will be a promising candidate for the low-power and appropriate performance apps in the next decade.

原文English
主出版物標題2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781509058051
DOIs
出版狀態Published - 7 六月 2017
事件2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017 - Hsinchu, Taiwan
持續時間: 24 四月 201727 四月 2017

出版系列

名字2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017

Conference

Conference2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
國家Taiwan
城市Hsinchu
期間24/04/1727/04/17

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