A novel 3D integration scheme for backside illuminated CMOS image sensor devices

Cheng Ta Ko, Zhi Cheng Hsiao, Hsiang Hung Chang, Dian Rong Lyu, Chao Kai Hsu, Huan Chun Fu, Chun Hsien Chien, Wei Chung Lo, Kuan-Neng Chen

研究成果: Article同行評審

9 引文 斯高帕斯(Scopus)

摘要

A novel backside-illuminated CMOS image sensor (BSI-CIS) scheme and process are developed and demonstrated. This innovative scheme can be realized without fusion oxide bonding and through-silicon via (TSV) fabrication. This wafer-level TSV-less BSI-CIS scheme includes transparent ultrathin silicon ∼3.6 μm and uses several bonding technologies. The characterization and assessment results indicate that the integration scheme possesses excellent electrical integrity and reliability. In addition, good quality results of the image functional test demonstrate the excellent performance of this scheme. This novel scheme also provides a realizable low-cost solution for the next-generation CIS and further 3-D novel BSI-CIS scheme.

原文English
文章編號6774458
頁(從 - 到)715-720
頁數6
期刊IEEE Transactions on Device and Materials Reliability
14
發行號2
DOIs
出版狀態Published - 1 一月 2014

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