In this paper, we propose a new two-dimensional (2-D) systolic-array digital filter using locally broadcast scheme that is the hybrid of a modified reordering and another systolic transformation. This architecture occupies locally broadcast, lower quantization error and zero latency without sacrificing the number of multipliers as well as delay elements under the accepted critical period. In addition, the widely used 2-D cascaded systolic digital filter can be described and reconstructed by similar methodology.
|出版狀態||Published - 1 十二月 2000|
|事件||2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems - Tianjin, China|
持續時間: 4 十二月 2000 → 6 十二月 2000
|Conference||2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems|
|期間||4/12/00 → 6/12/00|