A NAND flash memory controller for SD/MMC flash memory card

Chuan Sheng Lin*, Lan-Rong Dung

*Corresponding author for this work

研究成果: Article

12 引文 斯高帕斯(Scopus)

摘要

In this paper, a novel NAND flash memory controller was designed. A t-EC w-bit parallel Bose-Chaudhuri-Hoequengham (BCH) error-correction code (ECC) was designed for correcting the random bit errors of the flash memory chip, which is suitable for the randomly bit errors property and parallel I/O interface of the NAND-type flash memory. A code-banking mechanism was designed for the tradeoffs between the controller cost and the in-system programmability (ISP) support. With the ISP functionality and the Flash parameters programmed in the reserved area of the flash memory chip during the card production stage, the function for supporting various kinds of NAND flash memory could be provided by a single controller. In addition, built-in defect management and wear-leveling algorithm enhanced the product life cycle and reliability. Dual channel accessing of the Flash memory provided the good performance in data transfer rate. With respect to the proposed controller architecture, a real secure digital card (SD)/multimedia card (MMC) flash memory card controller chip was designed and implemented with UMC 0.18 μm CMOS process. Experimental results show the designed circuit can fully comply with the system specifications and shows the good performances.

原文English
頁(從 - 到)933-935
頁數3
期刊IEEE Transactions on Magnetics
43
發行號2
DOIs
出版狀態Published - 1 二月 2007

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