A MRMDF FFT processor for MIMO OFDM applications

Yu Wei Lin*, Wan Chun Liao, Chen Yi Lee

*Corresponding author for this work

研究成果: Conference contribution同行評審

摘要

In this paper, the proposed pipelined FFT processor, which is based on MRMDF structure, can deal with the simultaneous multiple input sequences more efficiently for MIMO OFDM applications. Furthermore, the hardware costs of memory and complex multipliers in our method can be saved by means of delay feedback and data scheduling approaches. The higher-radix FFT algorithm is also realized in our processor to reduce the number of complex multiplications. A test chip for 802.11n system has been designed using 0.13μm 1P8M CMOS process with core area of 2142×660 μm2. Power dissipation is 5.2mW when 128 points FFT with four data streams are calculated.

原文English
主出版物標題2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
發行者IEEE Computer Society
頁面225-228
頁數4
ISBN(列印)0780391624, 9780780391628
DOIs
出版狀態Published - 1 一月 2005
事件1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005 - Hsinchu, Taiwan
持續時間: 1 十一月 20053 十一月 2005

出版系列

名字2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Conference

Conference1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005
國家Taiwan
城市Hsinchu
期間1/11/053/11/05

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