A mixed-mode simulator for timing verification of analog-digital CMOS VLSI circuits is reported. It was developed by combining SPICE techniques for analog circuit simulation and gate-level techniques for digital circuit simulation based on the event-driven method. A new scheme called the block tearing (BT) approach at the macrocell level is proposed for memory storage savings while preserving reasonable accuracy. Benchmark tests of several example circuits show good performance in terms of speed and accuracy. The simulator is well suited for hierarchial VLSI circuits which are cell-based, such as current ASIC circuit design.