A mixed analog-digital simulator for ASIC using a novel block tearing approach

Steve S. Chung, J. L. Bie

研究成果: Conference contribution同行評審

摘要

A mixed-mode simulator for timing verification of analog-digital CMOS VLSI circuits is reported. It was developed by combining SPICE techniques for analog circuit simulation and gate-level techniques for digital circuit simulation based on the event-driven method. A new scheme called the block tearing (BT) approach at the macrocell level is proposed for memory storage savings while preserving reasonable accuracy. Benchmark tests of several example circuits show good performance in terms of speed and accuracy. The simulator is well suited for hierarchial VLSI circuits which are cell-based, such as current ASIC circuit design.

原文English
主出版物標題Proceedings - 6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993
發行者Institute of Electrical and Electronics Engineers Inc.
頁面527-530
頁數4
ISBN(電子)0780313755, 9780780313750
DOIs
出版狀態Published - 1 一月 1993
事件6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993 - Rochester, United States
持續時間: 27 九月 19931 十月 1993

出版系列

名字Proceedings - 6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993

Conference

Conference6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993
國家United States
城市Rochester
期間27/09/931/10/93

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