A micro-power two-step incremental analog-to-digital converter

Chia-Hung Chen, Yi Zhang, Tao He, Patrick Y. Chiang, Gabor C. Temes

研究成果: Article同行評審

44 引文 斯高帕斯(Scopus)

摘要

Integrated sensor interface circuits require energy-efficient high-resolution data converters. This paper proposes a two-step incremental A/D converter (IADC) which extends the performance of an Nth-order IADC close to that of a (2N-1)th-order IADC. The implemented device uses the circuitry of a second-order IADC (IADC2) to achieve close to third-order SNR performance. The proposed circuit does not require very high opamp DC gain; the gain can be as low as 60 dB for 100 dB SNR data conversion. The implemented IADC achieves a measured dynamic range of 99.8 dB, and an SNDR of 91 dB for a maximum input 2.2 VPP and a bandwidth of 250 Hz. Fabricated in 65 nm CMOS, the IADC's core area is 0.2 mm2 , and it consumes only 10.7 μW. The measured FoMs are 0.76 pJ/conversion and 173.5 dB, both among the best reported results for IADCs. The measured results verify that the proposed two-step IADC is a more energy-efficient data conversion scheme than conventional high-order IADCs.

原文English
文章編號7078971
頁(從 - 到)1796-1808
頁數13
期刊IEEE Journal of Solid-State Circuits
50
發行號8
DOIs
出版狀態Published - 1 八月 2015

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