A micro-network on chip with 10-Gb/s transmission link

Wei Chang Liu*, Chih Hsien Lin, Shyh-Jye Jou, Hung Wen Lu, Chau-Chin Su, Kai Wei Hong, Kuo Hsing Cheng, Shyue Wen Yang, Ming Hwa Sheu

*Corresponding author for this work

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

In this paper, a micro-network on chip (MNoC) with 10-Gb/s transmission link is proposed. A prototype system with two 5-port packet-based on-chip micro-switches and a 10-Gb/s data transceiver with an all digital data recovery circuit and a self-calibration clock generator are designed. This chip is implemented in 0.13μm CMOS technology. The core area of this chip is 990μm* 1600μm and the power consumption is 155mW (60mW for micro-switches and 95mW for 10-Gb/s data transceiver) at 1.2V supply voltage with 10-Gb/s transmission data rate.

原文English
主出版物標題Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
頁面277-280
頁數4
DOIs
出版狀態Published - 1 十二月 2009
事件2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 - Taipei, Taiwan
持續時間: 16 十一月 200918 十一月 2009

出版系列

名字Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

Conference

Conference2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
國家Taiwan
城市Taipei
期間16/11/0918/11/09

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  • 引用此

    Liu, W. C., Lin, C. H., Jou, S-J., Lu, H. W., Su, C-C., Hong, K. W., Cheng, K. H., Yang, S. W., & Sheu, M. H. (2009). A micro-network on chip with 10-Gb/s transmission link. 於 Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 (頁 277-280). [5357256] (Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009). https://doi.org/10.1109/ASSCC.2009.5357256