A memory efficient realization of cyclic convolution and its application to discrete cosine transform

Hun Chen Chen*, Jiun-In  Guo, Chein Wei Jen

*Corresponding author for this work

研究成果: Conference article同行評審

1 引文 斯高帕斯(Scopus)

摘要

This paper presents a memory efficient design for realizing the cyclic convolution and its application to the discrete cosine transform (DCT). We adopt the way of distributed arithmetic computation, and exploit the symmetry property of DCT coefficients to merge the elements in the matrix of DCT kernel and then separate the kernel to be two perfect cyclic forms to facilitate an efficient realization of 1-D N-point DCT using (N-1)/2 adders or substractors, one small ROM module, a barrel shifter, and N-1/2+1 accumulators. The comparison results with the existing designs show that the proposed design can reduce delay-area product significantly.

原文English
頁(從 - 到)33-36
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
4
DOIs
出版狀態Published - 14 七月 2003
事件Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand
持續時間: 25 五月 200328 五月 2003

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