A low-power vdd-management technique for high-speed domino circuits

Yu Tzu Tsai*, Hsiang Hui Huang, Sheng Wei Hsu, Ching Hwa Cheng, Jiun-In  Guo

*Corresponding author for this work

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

A low power voltage management technique is proposed to reduce power consumption for domino circuits. Exploiting a rising and charge-sharing voltage allow the domino circuits to have both high performance and low power consumption. A test chip has been successfully validated to achieve 68% dynamic power consumption and 15% static power consumption respectively using TSMC 0.13um CMOS technology.

原文English
主出版物標題Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
頁面394-397
頁數4
DOIs
出版狀態Published - 28 六月 2011
事件2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan
持續時間: 25 四月 201128 四月 2011

出版系列

名字Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

Conference

Conference2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
國家Taiwan
城市Hsinchu
期間25/04/1128/04/11

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