A low power programmable PRBS generator and a clock multiplier unit for 10 Gbps serdes applications

Wei-Zen Chen*, Guan Sheng Huang

*Corresponding author for this work

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

This paper presents the design of a low power programmable PRBS generator and a low noise clock multiplier unit (CMU) for 10 Gbps serdes applications. The PRBS generator is capable of producing 27-1, 210-1, 215-1, 223-1, and 231-1 b test pattern according to ITU-T recommendations. High speed and low power operations of the PRBS generator are achieved by 16 paths parallel feedback techniques. The measured jitter of the CMU is only 3.56 psrms, and the data jitter at the PRBS output is mainly determined by the CMU. Implemented in a 0.18μm CMOS process, the power dissipation for PRBS generator is only 10.8 mW, and the CMU consumes about 87mW.

原文English
主出版物標題ISCAS 2006
主出版物子標題2006 IEEE International Symposium on Circuits and Systems, Proceedings
頁面3273-3276
頁數4
DOIs
出版狀態Published - 1 十二月 2006
事件ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
持續時間: 21 五月 200624 五月 2006

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Conference

ConferenceISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
國家Greece
城市Kos
期間21/05/0624/05/06

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