A low-power, differential relaxation oscillator with the self-threshold-tracking and swing-boosting techniques in 0.18-μm CMOS

Shao Yung Lu*, Yu-Te Liao

*Corresponding author for this work

研究成果: Article同行評審

5 引文 斯高帕斯(Scopus)

摘要

This paper presents a fully integrated, 8.2-MHz relaxation oscillator with a self-threshold-tracking loop and swing-boosting technique for improving its long-term frequency stability and noise performance. The proposed latch-based relaxation oscillator increases the transition speed to reduce the static power consumption. To decrease the process-voltageerature dependence, we propose a self-threshold-tracking loop to ensure that the transition point of the inverter-based comparator is set to a fixed ratio of the supply voltage. In addition, the comparator delay can be compensated by the tracking loop, relaxing the requirements of comparator power consumption. The design is implemented in a 0.18-μm CMOS process. The design achieves a period jitter of 7.66 psrms, the phase noise of-109 dBc/Hz at an offset frequency of 100 kHz, and an Allan deviation noise floor of 1.56 ppm. The resultant figure of merit is 160.8 dBc/Hz, while only consuming 46.3 μW. The power efficiency of the design is 5.6 kHz/nW. As for the supply sensitivity, the design achieves 0.9 %/0.1 V, which is 10 × lower than the design with no compensation loop. The measured temperature coefficient of the proposed oscillators is 123 ppm/°C from-20 °C to 100 °C without any trimming process.

原文English
文章編號8558702
頁(從 - 到)392-402
頁數11
期刊IEEE Journal of Solid-State Circuits
54
發行號2
DOIs
出版狀態Published - 1 二月 2019

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