A lateral P-SI-N diode SPDT switch for Ka-band applications

Mitsuru Tanabe*, Junko Sato Iwanaga, Motonori Ishii, Kazuo Miyatsuji, Yorito Ota, Daisuke Ueda

*Corresponding author for this work

研究成果: Conference contribution

摘要

We report on lateral GaAs P-Semi-Insulator-N diode switches. The single P-Semi-Insulator-N structure showed the insertion loss of as low as 0.66 dB and the implemented SPDT switch that comprised the diodes exhibited the insertion loss of as low as 1.8 dB and isolation of 35 dB at 30 GHz. The proposed P-Semi-Insulator-N structure was easily formed by ion-implant technique and makes it possible to integrate with any active devices.

原文English
主出版物標題Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)
發行者IEEE
頁面263-266
頁數4
ISBN(列印)0780355865
DOIs
出版狀態Published - 1 十二月 1999
事件Proceedings of the 199 21st Annual IEEE Gallium Arsenide Integrated Circuit Symposium (IEEE GaAs IC Symposium) - Monterey, CA, USA
持續時間: 17 十月 199920 十月 1999

出版系列

名字Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)

Conference

ConferenceProceedings of the 199 21st Annual IEEE Gallium Arsenide Integrated Circuit Symposium (IEEE GaAs IC Symposium)
城市Monterey, CA, USA
期間17/10/9920/10/99

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