A highly reliable NAND structure flash memory capable for low voltage operation

Y. C. Lin*, C. S. Lai, Steve S. Chung, Evans Yang, S. Pittikoun, S. M. Tzeng, C. C.H. Hsu

*Corresponding author for this work

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

For the first time, a new flash cell called buried bit-line AND (BiAND) is proposed. Buried bit-line AND flash can achieve low voltage programming/erase. The major difference of the current flash cell from the conventional AND flash is the special design of a bit-line contact. With the use of the buried bit-line, the required high program/erase voltage for FN tunneling can be divided between the word-line and bit-line such that lower voltage operation is feasible. Further, the comparison of the cell reliability for different schemes, i.e., high voltage F-N (HV F-N) and Bi F-N operation schemes, has been studied. Results show that BiAND scheme gives much better endurance and data retention characteristics. This makes it successful for a low voltage and high reliability design.

原文English
主出版物標題2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual
頁面666-667
頁數2
DOIs
出版狀態Published - 15 十二月 2005
事件2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual - San Jose, CA, United States
持續時間: 17 四月 200521 四月 2005

出版系列

名字IEEE International Reliability Physics Symposium Proceedings
ISSN(列印)1541-7026

Conference

Conference2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual
國家United States
城市San Jose, CA
期間17/04/0521/04/05

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