A high throughput deblocking filter design supporting multiple video coding standards

Cheng An Chien*, Hsiu Cheng Chang, Jiun-In  Guo

*Corresponding author for this work

研究成果: Conference contribution同行評審

10 引文 斯高帕斯(Scopus)

摘要

This paper presents a high throughput, VLSI architecture for multi-standard in-loop deblocking filter (ILF) supporting H.264 BP/MP/HP, AVS, and VC-1 video decoding. It comprises 38.4Kgates and 672bytes of local memory using TSMC 0.13μm CMOS technology when operating at 225 MHz which meets the real-time processing requirement for high-resolution video decoding. We develop a PDB scheme and an integrated 1-D filter to realize various coding tools of the deblocking filter supporting multiple video coding standards.

原文English
主出版物標題2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
頁面2377-2380
頁數4
DOIs
出版狀態Published - 26 十月 2009
事件2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan
持續時間: 24 五月 200927 五月 2009

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Conference

Conference2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
國家Taiwan
城市Taipei
期間24/05/0927/05/09

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