A high throughput CAVLC design for HEVC

Hsuan Ku Chen*, Tian-Sheuan Chang

*Corresponding author for this work

研究成果: Paper同行評審

摘要

This paper proposes a high throughput context adaptive variable length coding (CAVLC) hardware design for high bit rate HEVC standard. The proposed design adopts a multi-coefficient encoding architecture with the input-parallel information-cascade method to solve the data dependency while attain high throughput. The final implementation with 90nm CMOS technology can process at least 3.2 coefficients per cycle with 12193 gate count when operate at 270MHz. This processing rate can support real video coding with 4Kx2K@60fps at the high bit rate case.

原文English
頁面1919-1922
頁數4
DOIs
出版狀態Published - 28 九月 2012
事件2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
持續時間: 20 五月 201223 五月 2012

Conference

Conference2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
國家Korea, Republic of
城市Seoul
期間20/05/1223/05/12

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