This study provides the experience of applying an advanced version of our former Spurious Power Suppression Technique (SPST) on multipliers for high-speed and low-power purposes. To filter out the useless switching power, there are two approaches, i.e. using registers and using AND gates, to assert the data signals of multipliers after the data transition. The simulation results show that the SPST implementation with AND gates owns an extremely high flexibility on adjusting the data asserting time which not only facilitates the robustness of SPST but also leads to a 40% speed improvement. By adopting a 0.18-μm CMOS technology, the proposed SPST-equipped multiplier dissipates only 0.0121 mW per MHz in H.264 texture coding applications, and obtains a 40% power reduction.
|頁（從 - 到）||3139-3142|
|期刊||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版狀態||Published - 27 九月 2007|
|事件||2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States|
持續時間: 27 五月 2007 → 30 五月 2007