A high speed Reed-Solomon decoder chip using inversionless decomposed architecture for Euclidean algorithm

Hsie-Chia Chang, Ching Che Chung, Chien Ching Lin, Chen-Yi Lee

研究成果: Conference article同行評審

3 引文 斯高帕斯(Scopus)

摘要

In this paper, a high speed Reed-Solomon (RS) decoder chip for optical communications is presented. It mainly contains one (255,239) RS decoder with 4K-bit embedded memory. Due to the operation speed limitation in I/O pad, a Delay Lock Loop (DLL) circuit is also included to generate internal high-speed clock. The RS decoder features a high speed and area-efficient key equation solver using a novel inversionless decomposed architecture for Euclidean algorithm. The test chip is implemented by 0.35μm CMOS SPQM standard cells with chip area of 2.61mm × 2.62mm. The RS decoder has the gate count of 12.4K. Test results show the proposed chip can support 2.35-Gbps data rate while operating at 294MHz with the supply voltage of 3.3V.

原文English
文章編號1471579
頁(從 - 到)519-522
頁數4
期刊European Solid-State Circuits Conference
出版狀態Published - 1 十二月 2002
事件28th European Solid-State Circuits Conference, ESSCIRC 2002 - Florence, Italy
持續時間: 24 九月 200226 九月 2002

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