A high-performance low power direct 2-D transform coding IP design for MPEG-4 AVC/H.264 with a switching power suppression technique

Kuan Hung Chen*, Jiun-In  Guo, Kuo Chuan Chao, Jinn Shyan Wang, Yuan Sun Chu

*Corresponding author for this work

研究成果: Conference contribution

12 引文 斯高帕斯(Scopus)

摘要

This paper proposes a high-performance low-power direct 2-D transform coding IP design for H.264 with a switching power suppression technique. The proposed transform coding design not only suitably arranges the data sequences in row and column transforms to greatly increase the data processing rate but also takes advantage of the correlation existed in natural video sequences to suppress the spurious switching power. When compared with the parallel transform architecture [2], this design possesses 4 times higher data processing rate (in terms of pixels/cycle) and 3.52 times higher throughput (in terms of pixels/sec) at the cost of 1.80 times hardware cost in computing the multi-transform for H.264. In addition, without voltage scaling, the power consumed by the proposed forward transform design is only 35% of that consumed by the forward transform design in [2] to maintain the same throughput. When the proposed switching power suppression technique is applied, the proposed transform design can perform digital cinema video coding format by consuming only 1.86 mW.

原文English
主出版物標題2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
頁面291-294
頁數4
DOIs
出版狀態Published - 1 十二月 2005
事件2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT) - Hsinchu, Taiwan
持續時間: 27 四月 200529 四月 2005

出版系列

名字2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
2005

Conference

Conference2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
國家Taiwan
城市Hsinchu
期間27/04/0529/04/05

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