A high performance liquid-nitrogen CMOS SRAM technology

J. Y.C. Sun*, S. Klepner, Y. Taur, H. Hanafi, P. Restle, T. Bucelot, K. Petrillo, R. Dennard, S. Schuster, T. Chappell, B. Chappell, D. Heidel

*Corresponding author for this work

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

A 3.5 ns ECL-compatible 64Kb liquid-nitrogen CMOS (LN-CMOS) SRAM technology with 2.5V power-supply voltage is described. Key features of this high performance 0.5μm-channel LN-CMOS SRAM technology optimized for 77K operation include 0.6,μm optical lithography for the gate level, dual polysilicon work functions, retrograde n-well, low resistance arsenic and boron source/drain diffusions, self-aligned titanium silicide, and two-level metal interconnects. For the first time, the leverage of liquid nitrogen CMOS with 2.3X chip level performance improvement at 77K over room temperature CMOS is demonstrated.

原文English
主出版物標題ESSDERC 1988 - 18th European Solid State Device Research Conference
編輯J.-P. Nougier, D. Gasquet
發行者IEEE Computer Society
頁面C425-C428
ISBN(電子)2868830994
ISBN(列印)9782868830999
出版狀態Published - 1988
事件18th European Solid State Device Research Conference, ESSDERC 1988 - Montpellier, France
持續時間: 13 九月 198816 九月 1988

出版系列

名字European Solid-State Device Research Conference
ISSN(列印)1930-8876

Conference

Conference18th European Solid State Device Research Conference, ESSDERC 1988
國家France
城市Montpellier
期間13/09/8816/09/88

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