A high-performance area-aware DSP processor architecture for video codecs

Lan-Da Van*, Hsin Fu Luo, Chien Ming Wu, Wen Hsiang Hu, Chun Ming Huang, Wei Chang Tsai

*Corresponding author for this work

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

In this paper, we propose a high-performance and area-aware very long instruction word (VLIW) DSP architecture using a flexible single instruction multiple data (SIMD) approach and a grouped permutation (GP) structure register file, respectively. Via the proposed data path architecture, the reduction of the execution cycles for digital filter and RGB2YUV benchmarks can be improved up to 50% compared with that of [8, 11]. For motion estimation, the number of pixels per cycle applying the proposed architecture can be four times than that of [8, 11]. For the register file, using proposed GP structure, the saving of switching network overhead could be anticipated compared with the work in [11].

原文English
主出版物標題2004 IEEE International Conference on Multimedia and Expo (ICME)
頁面1499-1502
頁數4
DOIs
出版狀態Published - 1 十二月 2004
事件2004 IEEE International Conference on Multimedia and Expo (ICME) - Taipei, Taiwan
持續時間: 27 六月 200430 六月 2004

出版系列

名字2004 IEEE International Conference on Multimedia and Expo (ICME)
3

Conference

Conference2004 IEEE International Conference on Multimedia and Expo (ICME)
國家Taiwan
城市Taipei
期間27/06/0430/06/04

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