A High-Density MOS Static RAM Cell Using the Lambda Bipolar Transistor

Chung-Yu Wu, Yih Fang Liu

研究成果: Article同行評審

7 引文 斯高帕斯(Scopus)

摘要

Based upon the common-collector lambda bipolar transistor (LBT), which is built with p-well NMOS, and the parasitic n-p-n BJT in a CMOS IC, a novel MOS static RAM cell called the LBT cell is proposed. In this new cell, the LBT and two poly-Si resistors form a bistable element with a PMOS access transistor. With the minimum feature size F, the optimal cell area of 32 F2 can be realized by using the silicide contact and small p-well spacing. The READ-WRITE operation is simulated. Due to the need of precharging before reading and the rather slow recovery after reading, suitable peripheral circuits should be designed.

原文English
頁(從 - 到)222-224
頁數3
期刊IEEE Journal of Solid-State Circuits
18
發行號2
DOIs
出版狀態Published - 1 一月 1983

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